1. Field of the Invention
The present invention relates to a chopper stabilized amplifier.
2. Description of the Related Art
The input offset voltage is one of the characteristics of an operational amplifier. An ideal operational amplifier has an input offset voltage (which is also referred to simply as an “offset voltage”) of zero. However, in actuality, an operational amplifier has a non-zero offset voltage. As a method for adjusting the offset voltage such that it becomes zero, a trimming method is known in which trimming is performed for every semiconductor chip in the manufacturing process such that its offset voltage becomes zero. However, such a trimming method has a problem of increased costs.
To cancel the offset voltage without the need for the trimming method, an operational amplifier that is referred to as a “chopper stabilized amplifier” or “auto-zero amplifier” has been proposed. FIG. 1 is a circuit diagram showing a chopper stabilized amplifier 200 investigated by the present inventors.
The chopper stabilized amplifier 200 amplifies the voltage difference between VP at a non-inverting input terminal (+) and VN at an inverting input terminal (−), and outputs an output signal SOUT via an output terminal OUT according to the voltage difference.
The chopper stabilized amplifier 200 includes a main amplifier 210 and a pair of correction amplifiers 220 and 230. The main amplifier 210 includes a differential input stage 212 and an output stage 214. The differential input stage 212 is configured as a gm amplifier (transconductance amplifier) having a non-zero offset voltage VOS1, for example. The output stage 214 converts a differential output of the differential input stage 212 into a single-ended signal.
The correction amplifiers 220 and 230, a current summing amplifier 240, and multiple switches SW21 and SW30 are provided in order to cancel out the offset voltage VOS1 of the main amplifier 210.
The multiple switches SW21 through SW30 alternately switch the state between a state A as shown in the drawing and a state B, which is a complementary state of the state A, according to a clock. In the state A, the first correction amplifier 220 corrects the offset voltage VOS1. In the state B, the second correction amplifier 230 corrects the offset voltage VOS1.
The correction amplifier 220 (230) includes a gm amplifier 222 (232) configured as a first stage and a gm amplifier 224 (234) configured as a second stage.
In the state A, the first-stage gm amplifier 222 of the first correction amplifier 220 receives the voltage VP at the non-inverting input terminal (+) and the voltage VN at the inverting input terminal (−), and amplifies the voltage difference between them. The output current of the gm amplifier 222 is converted into a voltage signal by means of capacitors C21 and C22 connected to the output terminals. The voltage signal thus converted is input to the current summing amplifier 240 via the switches SW25 and W26. The current summing amplifier 240 amplifies the voltage across the capacitor C21 and the voltage across the capacitor C22, and superimposes the differential current configured as the output of the gm amplifier 240 on the differential current output from the differential input stage 212 of the main amplifier 210.
In the state B, the first-stage gm amplifier 232 of the second correction amplifier 230 receives the voltage VP at the non-inverting input terminal (+) and the voltage VN at the inverting input terminal (−), and amplifies the voltage difference between them. The output current of the gm amplifier 232 is converted into a voltage signal by means of capacitors C23 and C24 connected to the output terminals. The voltage signal thus converted is input to the current summing amplifier 240 via the switches SW25 and W26. The current summing amplifier 240 amplifies the voltage across the capacitor C23 and the voltage across the capacitor C24, and superimposes the differential current configured as the output of the gm amplifier 240 on the differential current output from the differential input stage 212 of the main amplifier 210.
By repeatedly switching the state between the state A and the state B, such an arrangement is capable of canceling out the offset voltage VOS1 of the main amplifier 210.
However, the gm amplifiers 222 and 232, which are used for correction, also have non-zero offset voltages VOS2 and VOS3. In a case in which the offset voltages VOS2 and VOS3 are not negligible, such an arrangement is not capable of canceling out the offset voltage VOS1 with high precision. In order to cancel out the offset voltage VOS2 (VOS3), which is the offset of the correction amplifier 220 (230) itself, the second-stage gm amplifier 224 (234) feedback controls a bias current applied to the first-stage gm amplifier 222 such that the effect of the offset voltage VOS2 (VOS3) becomes zero.
Specifically, in the state A, the offset voltage VOS3 of the correction amplifier 230 is corrected. In the state B, the offset voltage VOS2 of the correction amplifier 220 is corrected. In the state A, the voltage difference between the differential input pair of the gm amplifier 232 is set to zero. In this state, the capacitors C23 and C24 connected to the output of the gm amplifier 232 provide a voltage difference that corresponds to the offset voltage VOS3. The second-stage gm amplifier 234 corrects the gm amplifier 232 such that the voltage difference that occurs between the capacitors C23 and C24 approaches zero.
The chopper stabilized amplifier 200 shown in FIG. 1 requires such multiple correction amplifiers 220 and 230, which is a problem. Furthermore, such an arrangement requires a complicated wiring pattern and a large circuit area, which is another problem.